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Macros</h2></td></tr>
<tr class="memitem:ga88e5d3fa1470e0fef0ae45c4956f1fa3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga88e5d3fa1470e0fef0ae45c4956f1fa3">XSrio_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga88e5d3fa1470e0fef0ae45c4956f1fa3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to read register.  <a href="group__srio__v1__0.html#ga88e5d3fa1470e0fef0ae45c4956f1fa3">More...</a><br /></td></tr>
<tr class="separator:ga88e5d3fa1470e0fef0ae45c4956f1fa3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f54b6fbef6410f2c375bde9e7bf09bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga7f54b6fbef6410f2c375bde9e7bf09bd">XSrio_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:ga7f54b6fbef6410f2c375bde9e7bf09bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to write register.  <a href="group__srio__v1__0.html#ga7f54b6fbef6410f2c375bde9e7bf09bd">More...</a><br /></td></tr>
<tr class="separator:ga7f54b6fbef6410f2c375bde9e7bf09bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr class="memitem:gabab5f1195566978a3b8d7547b6c4e0a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gabab5f1195566978a3b8d7547b6c4e0a3">XSRIO_DEV_ID_CAR_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gabab5f1195566978a3b8d7547b6c4e0a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Capability Address Register Space 0x00-0x3C Registers.  <a href="group__srio__v1__0.html#gabab5f1195566978a3b8d7547b6c4e0a3">More...</a><br /></td></tr>
<tr class="separator:gabab5f1195566978a3b8d7547b6c4e0a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad14b2c50e37ab6caeb26bd5677c1262a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gad14b2c50e37ab6caeb26bd5677c1262a">XSRIO_DEV_INFO_CAR_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gad14b2c50e37ab6caeb26bd5677c1262a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Information CAR.  <a href="group__srio__v1__0.html#gad14b2c50e37ab6caeb26bd5677c1262a">More...</a><br /></td></tr>
<tr class="separator:gad14b2c50e37ab6caeb26bd5677c1262a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1d21e2f268e2846ebe39b28a264f913"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gad1d21e2f268e2846ebe39b28a264f913">XSRIO_ASM_ID_CAR_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:gad1d21e2f268e2846ebe39b28a264f913"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assembly Identity CAR.  <a href="group__srio__v1__0.html#gad1d21e2f268e2846ebe39b28a264f913">More...</a><br /></td></tr>
<tr class="separator:gad1d21e2f268e2846ebe39b28a264f913"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a923d474a8eeac67f54d6259da07dc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga0a923d474a8eeac67f54d6259da07dc4">XSRIO_ASM_INFO_CAR_OFFSET</a>&#160;&#160;&#160;0x0C</td></tr>
<tr class="memdesc:ga0a923d474a8eeac67f54d6259da07dc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assembly Information CAR.  <a href="group__srio__v1__0.html#ga0a923d474a8eeac67f54d6259da07dc4">More...</a><br /></td></tr>
<tr class="separator:ga0a923d474a8eeac67f54d6259da07dc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1570a90db90ab3215174f7e6c40afebe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1570a90db90ab3215174f7e6c40afebe">XSRIO_PEF_CAR_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga1570a90db90ab3215174f7e6c40afebe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Processing Element Features CAR.  <a href="group__srio__v1__0.html#ga1570a90db90ab3215174f7e6c40afebe">More...</a><br /></td></tr>
<tr class="separator:ga1570a90db90ab3215174f7e6c40afebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga753b8bd0407c22845baa896f669fb275"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga753b8bd0407c22845baa896f669fb275">XSRIO_SWP_INFO_CAR_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga753b8bd0407c22845baa896f669fb275"><td class="mdescLeft">&#160;</td><td class="mdescRight">Switch Port Information CAR.  <a href="group__srio__v1__0.html#ga753b8bd0407c22845baa896f669fb275">More...</a><br /></td></tr>
<tr class="separator:ga753b8bd0407c22845baa896f669fb275"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ab414d1303bbb5d65e4a22a7361ea55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1ab414d1303bbb5d65e4a22a7361ea55">XSRIO_SRC_OPS_CAR_OFFSET</a>&#160;&#160;&#160;0x18</td></tr>
<tr class="memdesc:ga1ab414d1303bbb5d65e4a22a7361ea55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Source operations CAR.  <a href="group__srio__v1__0.html#ga1ab414d1303bbb5d65e4a22a7361ea55">More...</a><br /></td></tr>
<tr class="separator:ga1ab414d1303bbb5d65e4a22a7361ea55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d60eb0dc6cb85145be43d77bf14bae1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga6d60eb0dc6cb85145be43d77bf14bae1">XSRIO_DST_OPS_CAR_OFFSET</a>&#160;&#160;&#160;0x1c</td></tr>
<tr class="memdesc:ga6d60eb0dc6cb85145be43d77bf14bae1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Destination operations CAR.  <a href="group__srio__v1__0.html#ga6d60eb0dc6cb85145be43d77bf14bae1">More...</a><br /></td></tr>
<tr class="separator:ga6d60eb0dc6cb85145be43d77bf14bae1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b32c0953d0a478feea6138775413b63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2b32c0953d0a478feea6138775413b63">XSRIO_PELL_CTRL_CSR_OFFSET</a>&#160;&#160;&#160;0x4c</td></tr>
<tr class="memdesc:ga2b32c0953d0a478feea6138775413b63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command and Status Register Space 0x040-0xFC Registers.  <a href="group__srio__v1__0.html#ga2b32c0953d0a478feea6138775413b63">More...</a><br /></td></tr>
<tr class="separator:ga2b32c0953d0a478feea6138775413b63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2523f71ff70f2b70a144cd34df9f91e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2523f71ff70f2b70a144cd34df9f91e8">XSRIO_LCS0_BASEADDR_CSR_OFFSET</a>&#160;&#160;&#160;0x58</td></tr>
<tr class="memdesc:ga2523f71ff70f2b70a144cd34df9f91e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local Configuration Space 0 Base Address CSR.  <a href="group__srio__v1__0.html#ga2523f71ff70f2b70a144cd34df9f91e8">More...</a><br /></td></tr>
<tr class="separator:ga2523f71ff70f2b70a144cd34df9f91e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafffc5b4df1dd5366ef4074e68f7b958a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gafffc5b4df1dd5366ef4074e68f7b958a">XSRIO_LCS1_BASEADDR_CSR_OFFSET</a>&#160;&#160;&#160;0x5c</td></tr>
<tr class="memdesc:gafffc5b4df1dd5366ef4074e68f7b958a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local Configuration Space 1 Base Address CSR.  <a href="group__srio__v1__0.html#gafffc5b4df1dd5366ef4074e68f7b958a">More...</a><br /></td></tr>
<tr class="separator:gafffc5b4df1dd5366ef4074e68f7b958a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9b3abe05cc0b757413751f3c493023cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga9b3abe05cc0b757413751f3c493023cd">XSRIO_BASE_DID_CSR_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:ga9b3abe05cc0b757413751f3c493023cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Base Device ID CSR.  <a href="group__srio__v1__0.html#ga9b3abe05cc0b757413751f3c493023cd">More...</a><br /></td></tr>
<tr class="separator:ga9b3abe05cc0b757413751f3c493023cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa385c427eb29650bb31acbaf4a3e320c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaa385c427eb29650bb31acbaf4a3e320c">XSRIO_HOST_DID_LOCK_CSR_OFFSET</a>&#160;&#160;&#160;0x68</td></tr>
<tr class="memdesc:gaa385c427eb29650bb31acbaf4a3e320c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Host Base Device ID Lock CSR.  <a href="group__srio__v1__0.html#gaa385c427eb29650bb31acbaf4a3e320c">More...</a><br /></td></tr>
<tr class="separator:gaa385c427eb29650bb31acbaf4a3e320c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf538c58029dbfecbc051a594c5b6ab8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gabf538c58029dbfecbc051a594c5b6ab8">XSRIO_COMPONENT_TAG_CSR_OFFSET</a>&#160;&#160;&#160;0x6c</td></tr>
<tr class="memdesc:gabf538c58029dbfecbc051a594c5b6ab8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Component Tag CSR.  <a href="group__srio__v1__0.html#gabf538c58029dbfecbc051a594c5b6ab8">More...</a><br /></td></tr>
<tr class="separator:gabf538c58029dbfecbc051a594c5b6ab8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2e147a812705dfde71c8b3b5ea85b7e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2e147a812705dfde71c8b3b5ea85b7e0">XSRIO_EFB_HEADER_OFFSET</a>&#160;&#160;&#160;0x100</td></tr>
<tr class="memdesc:ga2e147a812705dfde71c8b3b5ea85b7e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Feature Register Space 0x0100-0xFFFC Registers.  <a href="group__srio__v1__0.html#ga2e147a812705dfde71c8b3b5ea85b7e0">More...</a><br /></td></tr>
<tr class="separator:ga2e147a812705dfde71c8b3b5ea85b7e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e79cd1c619b83e98fd3890a7e481afb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1e79cd1c619b83e98fd3890a7e481afb">XSRIO_PORT_LINK_TOUT_CSR_OFFSET</a>&#160;&#160;&#160;0x120</td></tr>
<tr class="memdesc:ga1e79cd1c619b83e98fd3890a7e481afb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Link Timeout CSR.  <a href="group__srio__v1__0.html#ga1e79cd1c619b83e98fd3890a7e481afb">More...</a><br /></td></tr>
<tr class="separator:ga1e79cd1c619b83e98fd3890a7e481afb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa2f205d7f2f3063e39ce45e6e2712bd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaa2f205d7f2f3063e39ce45e6e2712bd8">XSRIO_PORT_RESP_TOUT_CSR_OFFSET</a>&#160;&#160;&#160;0x124</td></tr>
<tr class="memdesc:gaa2f205d7f2f3063e39ce45e6e2712bd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Response Timeout CSR.  <a href="group__srio__v1__0.html#gaa2f205d7f2f3063e39ce45e6e2712bd8">More...</a><br /></td></tr>
<tr class="separator:gaa2f205d7f2f3063e39ce45e6e2712bd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4561044e5d4900706f43c752b43ff51a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4561044e5d4900706f43c752b43ff51a">XSRIO_PORT_GEN_CTL_CSR_OFFSET</a>&#160;&#160;&#160;0x13c</td></tr>
<tr class="memdesc:ga4561044e5d4900706f43c752b43ff51a"><td class="mdescLeft">&#160;</td><td class="mdescRight">General Control CSR.  <a href="group__srio__v1__0.html#ga4561044e5d4900706f43c752b43ff51a">More...</a><br /></td></tr>
<tr class="separator:ga4561044e5d4900706f43c752b43ff51a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98dd1aa546c28e3ad2e5dfa370795346"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga98dd1aa546c28e3ad2e5dfa370795346">XSRIO_PORT_N_MNT_REQ_CSR_OFFSET</a>&#160;&#160;&#160;0x140</td></tr>
<tr class="memdesc:ga98dd1aa546c28e3ad2e5dfa370795346"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port n Link Maintenance Request CSR.  <a href="group__srio__v1__0.html#ga98dd1aa546c28e3ad2e5dfa370795346">More...</a><br /></td></tr>
<tr class="separator:ga98dd1aa546c28e3ad2e5dfa370795346"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e71a8e128b15c1b237942a5485c1123"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8e71a8e128b15c1b237942a5485c1123">XSRIO_PORT_N_MNT_RES_CSR_OFFSET</a>&#160;&#160;&#160;0x144</td></tr>
<tr class="memdesc:ga8e71a8e128b15c1b237942a5485c1123"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port n Maintenance Response CSR.  <a href="group__srio__v1__0.html#ga8e71a8e128b15c1b237942a5485c1123">More...</a><br /></td></tr>
<tr class="separator:ga8e71a8e128b15c1b237942a5485c1123"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf43554809e5c07fffb0e53045b09c01c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaf43554809e5c07fffb0e53045b09c01c">XSRIO_PORT_N_ACKID_CSR_OFFSET</a>&#160;&#160;&#160;0x148</td></tr>
<tr class="memdesc:gaf43554809e5c07fffb0e53045b09c01c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port n Local Ack ID CSR.  <a href="group__srio__v1__0.html#gaf43554809e5c07fffb0e53045b09c01c">More...</a><br /></td></tr>
<tr class="separator:gaf43554809e5c07fffb0e53045b09c01c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa9bc2b856e9b7dcb4cd5781ec1df9681"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaa9bc2b856e9b7dcb4cd5781ec1df9681">XSRIO_PORT_N_ERR_STS_CSR_OFFSET</a>&#160;&#160;&#160;0x158</td></tr>
<tr class="memdesc:gaa9bc2b856e9b7dcb4cd5781ec1df9681"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port n Error and Status CSR.  <a href="group__srio__v1__0.html#gaa9bc2b856e9b7dcb4cd5781ec1df9681">More...</a><br /></td></tr>
<tr class="separator:gaa9bc2b856e9b7dcb4cd5781ec1df9681"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe2d28961f5aa630a30dc2916262d02b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gafe2d28961f5aa630a30dc2916262d02b">XSRIO_PORT_N_CTL_CSR_OFFSET</a>&#160;&#160;&#160;0x15c</td></tr>
<tr class="memdesc:gafe2d28961f5aa630a30dc2916262d02b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port n Control CSR.  <a href="group__srio__v1__0.html#gafe2d28961f5aa630a30dc2916262d02b">More...</a><br /></td></tr>
<tr class="separator:gafe2d28961f5aa630a30dc2916262d02b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72659b475911b0612f6bd8704ab1fe56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga72659b475911b0612f6bd8704ab1fe56">XSRIO_EFB_LPSL_OFFSET</a>&#160;&#160;&#160;0x0400</td></tr>
<tr class="memdesc:ga72659b475911b0612f6bd8704ab1fe56"><td class="mdescLeft">&#160;</td><td class="mdescRight">LP-Serial Lane Extended Features offset.  <a href="group__srio__v1__0.html#ga72659b475911b0612f6bd8704ab1fe56">More...</a><br /></td></tr>
<tr class="separator:ga72659b475911b0612f6bd8704ab1fe56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4499d2f039a465f34e8f80995c11b144"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4499d2f039a465f34e8f80995c11b144">XSRIO_SL_HEADER_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:ga4499d2f039a465f34e8f80995c11b144"><td class="mdescLeft">&#160;</td><td class="mdescRight">Serial Lane Block Header.  <a href="group__srio__v1__0.html#ga4499d2f039a465f34e8f80995c11b144">More...</a><br /></td></tr>
<tr class="separator:ga4499d2f039a465f34e8f80995c11b144"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1727fbcfcc856554646e9a8c037242b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gac1727fbcfcc856554646e9a8c037242b">XSRIO_SLS0_CSR_OFFSET</a>(n)&#160;&#160;&#160;(0x10 + n*0x20)</td></tr>
<tr class="memdesc:gac1727fbcfcc856554646e9a8c037242b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Serial Lane N Status 0 CSR.  <a href="group__srio__v1__0.html#gac1727fbcfcc856554646e9a8c037242b">More...</a><br /></td></tr>
<tr class="separator:gac1727fbcfcc856554646e9a8c037242b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29e13ba12fc174bbd8fcdf20f3fe0309"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga29e13ba12fc174bbd8fcdf20f3fe0309">XSRIO_SLS1_CSR_OFFSET</a>(n)&#160;&#160;&#160;(0x14 + n*0x20)</td></tr>
<tr class="memdesc:ga29e13ba12fc174bbd8fcdf20f3fe0309"><td class="mdescLeft">&#160;</td><td class="mdescRight">Serial Lane N Status 1 CSR.  <a href="group__srio__v1__0.html#ga29e13ba12fc174bbd8fcdf20f3fe0309">More...</a><br /></td></tr>
<tr class="separator:ga29e13ba12fc174bbd8fcdf20f3fe0309"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed9939e0409d3c884a5d6040818f30f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaed9939e0409d3c884a5d6040818f30f5">XSRIO_IMP_WCSR_OFFSET</a>&#160;&#160;&#160;0x10000</td></tr>
<tr class="memdesc:gaed9939e0409d3c884a5d6040818f30f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Implementation Defined Space 0x010000 - 0xFFFFFC Registers.  <a href="group__srio__v1__0.html#gaed9939e0409d3c884a5d6040818f30f5">More...</a><br /></td></tr>
<tr class="separator:gaed9939e0409d3c884a5d6040818f30f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad651fab42acba780368b1dbe153c1e4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gad651fab42acba780368b1dbe153c1e4d">XSRIO_IMP_BCSR_OFFSET</a>&#160;&#160;&#160;0x10004</td></tr>
<tr class="memdesc:gad651fab42acba780368b1dbe153c1e4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Control CSR.  <a href="group__srio__v1__0.html#gad651fab42acba780368b1dbe153c1e4d">More...</a><br /></td></tr>
<tr class="separator:gad651fab42acba780368b1dbe153c1e4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe4d77bd8382322b677d9765101c7b6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gafe4d77bd8382322b677d9765101c7b6d">XSRIO_IMP_MRIR_OFFSET</a>&#160;&#160;&#160;0x10100</td></tr>
<tr class="memdesc:gafe4d77bd8382322b677d9765101c7b6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maintenance Request Information Register.  <a href="group__srio__v1__0.html#gafe4d77bd8382322b677d9765101c7b6d">More...</a><br /></td></tr>
<tr class="separator:gafe4d77bd8382322b677d9765101c7b6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device Identity CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_DEV_ID_CAR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga5090e315c08229f3f0dd2f6da8a11d7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga5090e315c08229f3f0dd2f6da8a11d7b">XSRIO_DEV_ID_DEVID_CAR_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga5090e315c08229f3f0dd2f6da8a11d7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device ID Mask.  <a href="group__srio__v1__0.html#ga5090e315c08229f3f0dd2f6da8a11d7b">More...</a><br /></td></tr>
<tr class="separator:ga5090e315c08229f3f0dd2f6da8a11d7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39ae0182ccd2af230e7c1b9a308f8fdd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga39ae0182ccd2af230e7c1b9a308f8fdd">XSRIO_DEV_ID_VDRID_CAR_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga39ae0182ccd2af230e7c1b9a308f8fdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Vendor ID Mask.  <a href="group__srio__v1__0.html#ga39ae0182ccd2af230e7c1b9a308f8fdd">More...</a><br /></td></tr>
<tr class="separator:ga39ae0182ccd2af230e7c1b9a308f8fdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga820df48ad6186de84f3140bf90383c10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga820df48ad6186de84f3140bf90383c10">XSRIO_DEV_ID_DEVID_CAR_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga820df48ad6186de84f3140bf90383c10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device ID shift.  <a href="group__srio__v1__0.html#ga820df48ad6186de84f3140bf90383c10">More...</a><br /></td></tr>
<tr class="separator:ga820df48ad6186de84f3140bf90383c10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device Information CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_DEV_INFO_CAR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:gab9ba3c9cdef8014cda81ad9130097499"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab9ba3c9cdef8014cda81ad9130097499">XSRIO_DEV_INFO_CAR_PATCH_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:gab9ba3c9cdef8014cda81ad9130097499"><td class="mdescLeft">&#160;</td><td class="mdescRight">Patch Mask.  <a href="group__srio__v1__0.html#gab9ba3c9cdef8014cda81ad9130097499">More...</a><br /></td></tr>
<tr class="separator:gab9ba3c9cdef8014cda81ad9130097499"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae816b6c8a6fbdc0972f3dc8119c3178c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gae816b6c8a6fbdc0972f3dc8119c3178c">XSRIO_DEV_INFO_CAR_MINREV_MASK</a>&#160;&#160;&#160;0x000000F0</td></tr>
<tr class="memdesc:gae816b6c8a6fbdc0972f3dc8119c3178c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Minor Revision Mask.  <a href="group__srio__v1__0.html#gae816b6c8a6fbdc0972f3dc8119c3178c">More...</a><br /></td></tr>
<tr class="separator:gae816b6c8a6fbdc0972f3dc8119c3178c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga57bbd05c855900c98c37ff0cb47d7753"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga57bbd05c855900c98c37ff0cb47d7753">XSRIO_DEV_INFO_CAR_MAJREV_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:ga57bbd05c855900c98c37ff0cb47d7753"><td class="mdescLeft">&#160;</td><td class="mdescRight">Major Revision Mask.  <a href="group__srio__v1__0.html#ga57bbd05c855900c98c37ff0cb47d7753">More...</a><br /></td></tr>
<tr class="separator:ga57bbd05c855900c98c37ff0cb47d7753"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1519b0fad8875ce6e1914f9015b34c97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1519b0fad8875ce6e1914f9015b34c97">XSRIO_DEV_INFO_CAR_DEVREV_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:ga1519b0fad8875ce6e1914f9015b34c97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Revision Lable Mask.  <a href="group__srio__v1__0.html#ga1519b0fad8875ce6e1914f9015b34c97">More...</a><br /></td></tr>
<tr class="separator:ga1519b0fad8875ce6e1914f9015b34c97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Assembly Identity CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_ASM_ID_CAR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga89b8ef844db7e44d64e664cd6db8be32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga89b8ef844db7e44d64e664cd6db8be32">XSRIO_ASM_ID_CAR_ASMID_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga89b8ef844db7e44d64e664cd6db8be32"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assembly ID Mask.  <a href="group__srio__v1__0.html#ga89b8ef844db7e44d64e664cd6db8be32">More...</a><br /></td></tr>
<tr class="separator:ga89b8ef844db7e44d64e664cd6db8be32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd35ed24ff26b397f6c1631c92782f3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gadd35ed24ff26b397f6c1631c92782f3b">XSRIO_ASM_ID_CAR_ASMVID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gadd35ed24ff26b397f6c1631c92782f3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assembly Vendor ID Mask.  <a href="group__srio__v1__0.html#gadd35ed24ff26b397f6c1631c92782f3b">More...</a><br /></td></tr>
<tr class="separator:gadd35ed24ff26b397f6c1631c92782f3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1cd5b1b731cd9b62308620bfb57e3fb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1cd5b1b731cd9b62308620bfb57e3fb3">XSRIO_ASM_ID_CAR_ASMID_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga1cd5b1b731cd9b62308620bfb57e3fb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assembly ID Shift.  <a href="group__srio__v1__0.html#ga1cd5b1b731cd9b62308620bfb57e3fb3">More...</a><br /></td></tr>
<tr class="separator:ga1cd5b1b731cd9b62308620bfb57e3fb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Assembly Device Information CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_ASM_INFO_CAR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga227ff52b5cef4a3e6580d8f4f9eb804b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga227ff52b5cef4a3e6580d8f4f9eb804b">XSRIO_ASM_INFO_CAR_ASMREV_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga227ff52b5cef4a3e6580d8f4f9eb804b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assembly Revision Mask.  <a href="group__srio__v1__0.html#ga227ff52b5cef4a3e6580d8f4f9eb804b">More...</a><br /></td></tr>
<tr class="separator:ga227ff52b5cef4a3e6580d8f4f9eb804b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7548def33dd41ea582a382c7ffbe2c58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga7548def33dd41ea582a382c7ffbe2c58">XSRIO_ASM_INFO_CAR_EFP_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga7548def33dd41ea582a382c7ffbe2c58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features Pointer Mask.  <a href="group__srio__v1__0.html#ga7548def33dd41ea582a382c7ffbe2c58">More...</a><br /></td></tr>
<tr class="separator:ga7548def33dd41ea582a382c7ffbe2c58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7253ac10f0978d022f8a89ff6c11763b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga7253ac10f0978d022f8a89ff6c11763b">XSRIO_ASM_INFO_CAR_ASMREV_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga7253ac10f0978d022f8a89ff6c11763b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assembly Revision Shift.  <a href="group__srio__v1__0.html#ga7253ac10f0978d022f8a89ff6c11763b">More...</a><br /></td></tr>
<tr class="separator:ga7253ac10f0978d022f8a89ff6c11763b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Processing Element Features CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PEF_CAR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga2d6b158355390bd7f0b0ade352521085"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2d6b158355390bd7f0b0ade352521085">XSRIO_PEF_CAR_EAS_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:ga2d6b158355390bd7f0b0ade352521085"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Addressing Support Mask.  <a href="group__srio__v1__0.html#ga2d6b158355390bd7f0b0ade352521085">More...</a><br /></td></tr>
<tr class="separator:ga2d6b158355390bd7f0b0ade352521085"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac93d1ac843017fa14ef476016ca5a493"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gac93d1ac843017fa14ef476016ca5a493">XSRIO_PEF_CAR_EF_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gac93d1ac843017fa14ef476016ca5a493"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features Mask.  <a href="group__srio__v1__0.html#gac93d1ac843017fa14ef476016ca5a493">More...</a><br /></td></tr>
<tr class="separator:gac93d1ac843017fa14ef476016ca5a493"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d0954eda8d0276d5555eee23fa85d6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga6d0954eda8d0276d5555eee23fa85d6c">XSRIO_PEF_CAR_CTS_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga6d0954eda8d0276d5555eee23fa85d6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common Transport Large System support Mask.  <a href="group__srio__v1__0.html#ga6d0954eda8d0276d5555eee23fa85d6c">More...</a><br /></td></tr>
<tr class="separator:ga6d0954eda8d0276d5555eee23fa85d6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae8b2866d05745c18564ad1ac6f9fefb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaae8b2866d05745c18564ad1ac6f9fefb">XSRIO_PEF_CAR_CRF_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gaae8b2866d05745c18564ad1ac6f9fefb"><td class="mdescLeft">&#160;</td><td class="mdescRight">CRF Support Mask.  <a href="group__srio__v1__0.html#gaae8b2866d05745c18564ad1ac6f9fefb">More...</a><br /></td></tr>
<tr class="separator:gaae8b2866d05745c18564ad1ac6f9fefb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0a3a94ae53c3cc2fdc92c76ca5c353e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaf0a3a94ae53c3cc2fdc92c76ca5c353e">XSRIO_PEF_CAR_MPORT_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:gaf0a3a94ae53c3cc2fdc92c76ca5c353e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi Port Mask.  <a href="group__srio__v1__0.html#gaf0a3a94ae53c3cc2fdc92c76ca5c353e">More...</a><br /></td></tr>
<tr class="separator:gaf0a3a94ae53c3cc2fdc92c76ca5c353e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a1b0962ee0ebaa929ccb86c4ace33de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4a1b0962ee0ebaa929ccb86c4ace33de">XSRIO_PEF_CAR_SWITCH_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:ga4a1b0962ee0ebaa929ccb86c4ace33de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Switch Mask.  <a href="group__srio__v1__0.html#ga4a1b0962ee0ebaa929ccb86c4ace33de">More...</a><br /></td></tr>
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<tr class="memitem:ga621c66a2f36ea07e5b82ba99f57f03d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga621c66a2f36ea07e5b82ba99f57f03d6">XSRIO_PEF_CAR_PROCESSOR_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:ga621c66a2f36ea07e5b82ba99f57f03d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Processor Mask.  <a href="group__srio__v1__0.html#ga621c66a2f36ea07e5b82ba99f57f03d6">More...</a><br /></td></tr>
<tr class="separator:ga621c66a2f36ea07e5b82ba99f57f03d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b13843464edf06633294d148150830d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2b13843464edf06633294d148150830d">XSRIO_PEF_CAR_MEMORY_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga2b13843464edf06633294d148150830d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory Mask.  <a href="group__srio__v1__0.html#ga2b13843464edf06633294d148150830d">More...</a><br /></td></tr>
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<tr class="memitem:gafa5c4fef269eeda1a92245050eaef59c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gafa5c4fef269eeda1a92245050eaef59c">XSRIO_PEF_CAR_BRIDGE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gafa5c4fef269eeda1a92245050eaef59c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Mask.  <a href="group__srio__v1__0.html#gafa5c4fef269eeda1a92245050eaef59c">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Source Operations CAR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SRC_OPS_CAR_OFFSET register and XSRIO_DST_OPS_CAR register. </p>
</div></td></tr>
<tr class="memitem:ga8737d4f9b2bbb4967c23db9f9fa6be93"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8737d4f9b2bbb4967c23db9f9fa6be93">XSRIO_SRCDST_OPS_CAR_PORT_WRITE_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga8737d4f9b2bbb4967c23db9f9fa6be93"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port write operation Mask.  <a href="group__srio__v1__0.html#ga8737d4f9b2bbb4967c23db9f9fa6be93">More...</a><br /></td></tr>
<tr class="separator:ga8737d4f9b2bbb4967c23db9f9fa6be93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0264576cb706923cec5995efe3099cba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga0264576cb706923cec5995efe3099cba">XSRIO_SRCDST_OPS_CAR_ATOMIC_SWP_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga0264576cb706923cec5995efe3099cba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomic Swap Mask.  <a href="group__srio__v1__0.html#ga0264576cb706923cec5995efe3099cba">More...</a><br /></td></tr>
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<tr class="memitem:gadbe14155da68eb261b8358917fbe4b28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gadbe14155da68eb261b8358917fbe4b28">XSRIO_SRCDST_OPS_CAR_ATOMIC_CLR_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gadbe14155da68eb261b8358917fbe4b28"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomic Clear Mask.  <a href="group__srio__v1__0.html#gadbe14155da68eb261b8358917fbe4b28">More...</a><br /></td></tr>
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<tr class="memitem:gabf5a63a4034d3c3814841ad90a75bfe4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gabf5a63a4034d3c3814841ad90a75bfe4">XSRIO_SRCDST_OPS_CAR_ATOMIC_SET_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gabf5a63a4034d3c3814841ad90a75bfe4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomic Set Mask.  <a href="group__srio__v1__0.html#gabf5a63a4034d3c3814841ad90a75bfe4">More...</a><br /></td></tr>
<tr class="separator:gabf5a63a4034d3c3814841ad90a75bfe4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e04947da2ff98cbf2f671b53b0405fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga9e04947da2ff98cbf2f671b53b0405fb">XSRIO_SRCDST_OPS_CAR_ATOMIC_DECR_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga9e04947da2ff98cbf2f671b53b0405fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomic Decrement Mask.  <a href="group__srio__v1__0.html#ga9e04947da2ff98cbf2f671b53b0405fb">More...</a><br /></td></tr>
<tr class="separator:ga9e04947da2ff98cbf2f671b53b0405fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6664e5a03ee2cd53fd940c7f45f3bbf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gac6664e5a03ee2cd53fd940c7f45f3bbf">XSRIO_SRCDST_OPS_CAR_ATOMIC_INCR_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gac6664e5a03ee2cd53fd940c7f45f3bbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomic Increment Mask.  <a href="group__srio__v1__0.html#gac6664e5a03ee2cd53fd940c7f45f3bbf">More...</a><br /></td></tr>
<tr class="separator:gac6664e5a03ee2cd53fd940c7f45f3bbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b58f817ee4df7f2ce15b7bb8d0d9be4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga7b58f817ee4df7f2ce15b7bb8d0d9be4">XSRIO_SRCDST_OPS_CAR_ATOMIC_TSWP_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga7b58f817ee4df7f2ce15b7bb8d0d9be4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomic test and swap Mask.  <a href="group__srio__v1__0.html#ga7b58f817ee4df7f2ce15b7bb8d0d9be4">More...</a><br /></td></tr>
<tr class="separator:ga7b58f817ee4df7f2ce15b7bb8d0d9be4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8eddbe65450de7f46d151873236ab470"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8eddbe65450de7f46d151873236ab470">XSRIO_SRCDST_OPS_CAR_ATOMIC_CSWP_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga8eddbe65450de7f46d151873236ab470"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomic compare and Swap Mask.  <a href="group__srio__v1__0.html#ga8eddbe65450de7f46d151873236ab470">More...</a><br /></td></tr>
<tr class="separator:ga8eddbe65450de7f46d151873236ab470"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4b33820d42c378851f2dbdd566d49bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gad4b33820d42c378851f2dbdd566d49bd">XSRIO_SRCDST_OPS_CAR_DOORBELL_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:gad4b33820d42c378851f2dbdd566d49bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Doorbell Mask.  <a href="group__srio__v1__0.html#gad4b33820d42c378851f2dbdd566d49bd">More...</a><br /></td></tr>
<tr class="separator:gad4b33820d42c378851f2dbdd566d49bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9a8a2832415e8c971d2041493565717"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaf9a8a2832415e8c971d2041493565717">XSRIO_SRCDST_OPS_CAR_DATA_MSG_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:gaf9a8a2832415e8c971d2041493565717"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Message Mask.  <a href="group__srio__v1__0.html#gaf9a8a2832415e8c971d2041493565717">More...</a><br /></td></tr>
<tr class="separator:gaf9a8a2832415e8c971d2041493565717"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a3f3c7eac1bf613ee6357d54c871f18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8a3f3c7eac1bf613ee6357d54c871f18">XSRIO_SRCDST_OPS_CAR_WRITE_RESPONSE_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga8a3f3c7eac1bf613ee6357d54c871f18"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write with Response Mask.  <a href="group__srio__v1__0.html#ga8a3f3c7eac1bf613ee6357d54c871f18">More...</a><br /></td></tr>
<tr class="separator:ga8a3f3c7eac1bf613ee6357d54c871f18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d9cbc1037e2dd1ab3a902699e12e5a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga3d9cbc1037e2dd1ab3a902699e12e5a1">XSRIO_SRCDST_OPS_CAR_SWRITE_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:ga3d9cbc1037e2dd1ab3a902699e12e5a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Write Mask.  <a href="group__srio__v1__0.html#ga3d9cbc1037e2dd1ab3a902699e12e5a1">More...</a><br /></td></tr>
<tr class="separator:ga3d9cbc1037e2dd1ab3a902699e12e5a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga368e473b38c87a7845e43ed0b83c4bb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga368e473b38c87a7845e43ed0b83c4bb4">XSRIO_SRCDST_OPS_CAR_WRITE_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:ga368e473b38c87a7845e43ed0b83c4bb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write Mask.  <a href="group__srio__v1__0.html#ga368e473b38c87a7845e43ed0b83c4bb4">More...</a><br /></td></tr>
<tr class="separator:ga368e473b38c87a7845e43ed0b83c4bb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22a5bbcfc74d7e895fc806b26a648a62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga22a5bbcfc74d7e895fc806b26a648a62">XSRIO_SRCDST_OPS_CAR_READ_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ga22a5bbcfc74d7e895fc806b26a648a62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Mask.  <a href="group__srio__v1__0.html#ga22a5bbcfc74d7e895fc806b26a648a62">More...</a><br /></td></tr>
<tr class="separator:ga22a5bbcfc74d7e895fc806b26a648a62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">PE Logical layer Control CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PELL_CTRL_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga0966efd0126d91bb7d471a290a0a337f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga0966efd0126d91bb7d471a290a0a337f">XSRIO_PELL_CTRL_CSR_EAC_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:ga0966efd0126d91bb7d471a290a0a337f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Addressing Control Mask.  <a href="group__srio__v1__0.html#ga0966efd0126d91bb7d471a290a0a337f">More...</a><br /></td></tr>
<tr class="separator:ga0966efd0126d91bb7d471a290a0a337f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Local Configuration Space Base Address 1 CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_LCS1_BASEADDR_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga7c4c40c3d4edc4ca1bc643c95fe18cf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga7c4c40c3d4edc4ca1bc643c95fe18cf2">XSRIO_LCS1_BASEADDR_LCSBA_CSR_MASK</a>&#160;&#160;&#160;0x7FE00000</td></tr>
<tr class="memdesc:ga7c4c40c3d4edc4ca1bc643c95fe18cf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">LCSBA Mask.  <a href="group__srio__v1__0.html#ga7c4c40c3d4edc4ca1bc643c95fe18cf2">More...</a><br /></td></tr>
<tr class="separator:ga7c4c40c3d4edc4ca1bc643c95fe18cf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacffff28710d77ac7a123f78728eb4712"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gacffff28710d77ac7a123f78728eb4712">XSRIO_LCS1_BASEADDR_LCSBA_CSR_SHIFT</a>&#160;&#160;&#160;21</td></tr>
<tr class="memdesc:gacffff28710d77ac7a123f78728eb4712"><td class="mdescLeft">&#160;</td><td class="mdescRight">LCSBA Shift.  <a href="group__srio__v1__0.html#gacffff28710d77ac7a123f78728eb4712">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Base Device ID CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_BASE_DID_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga593eed7b4e0cf5c113668ec501709392"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga593eed7b4e0cf5c113668ec501709392">XSRIO_BASE_DID_CSR_LBDID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga593eed7b4e0cf5c113668ec501709392"><td class="mdescLeft">&#160;</td><td class="mdescRight">Large Base Device ID Mask(16-bit device ID)  <a href="group__srio__v1__0.html#ga593eed7b4e0cf5c113668ec501709392">More...</a><br /></td></tr>
<tr class="separator:ga593eed7b4e0cf5c113668ec501709392"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa398a9d87c352370ad8368def9aec0df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaa398a9d87c352370ad8368def9aec0df">XSRIO_BASE_DID_CSR_BDID_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gaa398a9d87c352370ad8368def9aec0df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Base Device ID Mask(8-bit device ID)  <a href="group__srio__v1__0.html#gaa398a9d87c352370ad8368def9aec0df">More...</a><br /></td></tr>
<tr class="separator:gaa398a9d87c352370ad8368def9aec0df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd5f5e46e978b7addcd450362a3e4f6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gadd5f5e46e978b7addcd450362a3e4f6b">XSRIO_BASE_DID_CSR_BDID_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gadd5f5e46e978b7addcd450362a3e4f6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Base Device ID Shift.  <a href="group__srio__v1__0.html#gadd5f5e46e978b7addcd450362a3e4f6b">More...</a><br /></td></tr>
<tr class="separator:gadd5f5e46e978b7addcd450362a3e4f6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Host Base Device ID CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_HOST_DID_LOCK_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga65ffdf1055349f408681a28e4804ad0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga65ffdf1055349f408681a28e4804ad0a">XSRIO_HOST_DID_LOCK_CSR_HBDID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga65ffdf1055349f408681a28e4804ad0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Host Base Device ID Mask.  <a href="group__srio__v1__0.html#ga65ffdf1055349f408681a28e4804ad0a">More...</a><br /></td></tr>
<tr class="separator:ga65ffdf1055349f408681a28e4804ad0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">LP - Serial Register Block header bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_EFB_HEADER_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga6cdfee54edff28e0f650ca0e6be5f69f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga6cdfee54edff28e0f650ca0e6be5f69f">XSRIO_EFB_HEADER_EFID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga6cdfee54edff28e0f650ca0e6be5f69f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features ID Mask.  <a href="group__srio__v1__0.html#ga6cdfee54edff28e0f650ca0e6be5f69f">More...</a><br /></td></tr>
<tr class="separator:ga6cdfee54edff28e0f650ca0e6be5f69f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab268d0f09ad1647741b2db233c436cfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab268d0f09ad1647741b2db233c436cfa">XSRIO_EFB_HEADER_EFP_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:gab268d0f09ad1647741b2db233c436cfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features Pointer Mask.  <a href="group__srio__v1__0.html#gab268d0f09ad1647741b2db233c436cfa">More...</a><br /></td></tr>
<tr class="separator:gab268d0f09ad1647741b2db233c436cfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa8021afc163a4658898e6f036b7f50ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaa8021afc163a4658898e6f036b7f50ca">XSRIO_EFB_HEADER_EFP_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gaa8021afc163a4658898e6f036b7f50ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features Pointer Shift.  <a href="group__srio__v1__0.html#gaa8021afc163a4658898e6f036b7f50ca">More...</a><br /></td></tr>
<tr class="separator:gaa8021afc163a4658898e6f036b7f50ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port Link timeout value CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_LINK_TOUT_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga4879c96774b975189fcbf586e57a06ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4879c96774b975189fcbf586e57a06ba">XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_MASK</a>&#160;&#160;&#160;0xFFFFFF00</td></tr>
<tr class="memdesc:ga4879c96774b975189fcbf586e57a06ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timeout Value Mask.  <a href="group__srio__v1__0.html#ga4879c96774b975189fcbf586e57a06ba">More...</a><br /></td></tr>
<tr class="separator:ga4879c96774b975189fcbf586e57a06ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1393da4ef49e86fc2372cc7da2c7f1f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1393da4ef49e86fc2372cc7da2c7f1f2">XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga1393da4ef49e86fc2372cc7da2c7f1f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timeout Value Shift.  <a href="group__srio__v1__0.html#ga1393da4ef49e86fc2372cc7da2c7f1f2">More...</a><br /></td></tr>
<tr class="separator:ga1393da4ef49e86fc2372cc7da2c7f1f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port response timeout value CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_RESP_TOUT_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga14f32634f2bedb6a547b75714ab1300a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga14f32634f2bedb6a547b75714ab1300a">XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_MASK</a>&#160;&#160;&#160;0xFFFFFF00</td></tr>
<tr class="memdesc:ga14f32634f2bedb6a547b75714ab1300a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Response Timeout Value Mask.  <a href="group__srio__v1__0.html#ga14f32634f2bedb6a547b75714ab1300a">More...</a><br /></td></tr>
<tr class="separator:ga14f32634f2bedb6a547b75714ab1300a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc4dcceafc76cc3725fdcee33bda63e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gacc4dcceafc76cc3725fdcee33bda63e8">XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gacc4dcceafc76cc3725fdcee33bda63e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Response Timeout Shift.  <a href="group__srio__v1__0.html#gacc4dcceafc76cc3725fdcee33bda63e8">More...</a><br /></td></tr>
<tr class="separator:gacc4dcceafc76cc3725fdcee33bda63e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port General Control CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_GEN_CTL_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga39dba66c3b45c23056552d38459a5426"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga39dba66c3b45c23056552d38459a5426">XSRIO_PORT_GEN_CTL_CSR_DISCOVERED_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:ga39dba66c3b45c23056552d38459a5426"><td class="mdescLeft">&#160;</td><td class="mdescRight">Discovered Mask.  <a href="group__srio__v1__0.html#ga39dba66c3b45c23056552d38459a5426">More...</a><br /></td></tr>
<tr class="separator:ga39dba66c3b45c23056552d38459a5426"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga008f961f9e1d2c969c8cf9a4b886e3d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga008f961f9e1d2c969c8cf9a4b886e3d6">XSRIO_PORT_GEN_CTL_CSR_MENABLE_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga008f961f9e1d2c969c8cf9a4b886e3d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Enable Mask.  <a href="group__srio__v1__0.html#ga008f961f9e1d2c969c8cf9a4b886e3d6">More...</a><br /></td></tr>
<tr class="separator:ga008f961f9e1d2c969c8cf9a4b886e3d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77b8c4f3f9031effb14a67997d224677"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga77b8c4f3f9031effb14a67997d224677">XSRIO_PORT_GEN_CTL_CSR_HOST_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga77b8c4f3f9031effb14a67997d224677"><td class="mdescLeft">&#160;</td><td class="mdescRight">Host Mask.  <a href="group__srio__v1__0.html#ga77b8c4f3f9031effb14a67997d224677">More...</a><br /></td></tr>
<tr class="separator:ga77b8c4f3f9031effb14a67997d224677"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n maintenance request CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_MNT_REQ_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga90f9f21f13d053d8d92578cdddfe8027"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga90f9f21f13d053d8d92578cdddfe8027">XSRIO_PORT_N_MNT_REQ_CSR_CMD_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:ga90f9f21f13d053d8d92578cdddfe8027"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Mask.  <a href="group__srio__v1__0.html#ga90f9f21f13d053d8d92578cdddfe8027">More...</a><br /></td></tr>
<tr class="separator:ga90f9f21f13d053d8d92578cdddfe8027"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n maintenance response CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_MNT_RES_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:gaca75fd651b951142907705655e182748"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaca75fd651b951142907705655e182748">XSRIO_PORT_N_MNT_RES_CSR_LS_MASK</a>&#160;&#160;&#160;0x0000001F</td></tr>
<tr class="memdesc:gaca75fd651b951142907705655e182748"><td class="mdescLeft">&#160;</td><td class="mdescRight">link status Mask  <a href="group__srio__v1__0.html#gaca75fd651b951142907705655e182748">More...</a><br /></td></tr>
<tr class="separator:gaca75fd651b951142907705655e182748"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35d6f6638ce1eb8c47faff00fdbed6b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga35d6f6638ce1eb8c47faff00fdbed6b9">XSRIO_PORT_N_MNT_RES_CSR_ACKS_MASK</a>&#160;&#160;&#160;0x000007E0</td></tr>
<tr class="memdesc:ga35d6f6638ce1eb8c47faff00fdbed6b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ack ID status Mask.  <a href="group__srio__v1__0.html#ga35d6f6638ce1eb8c47faff00fdbed6b9">More...</a><br /></td></tr>
<tr class="separator:ga35d6f6638ce1eb8c47faff00fdbed6b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga823f5fff998236f34c384e1a6e3450d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga823f5fff998236f34c384e1a6e3450d8">XSRIO_PORT_N_MNT_RES_CSR_RVALID_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga823f5fff998236f34c384e1a6e3450d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Response Valid Mask.  <a href="group__srio__v1__0.html#ga823f5fff998236f34c384e1a6e3450d8">More...</a><br /></td></tr>
<tr class="separator:ga823f5fff998236f34c384e1a6e3450d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n local ack ID CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_ACKID_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga6541e592e664f2549721d2073626dc91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga6541e592e664f2549721d2073626dc91">XSRIO_PORT_N_ACKID_CSR_OBACKID_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:ga6541e592e664f2549721d2073626dc91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Out bound ACK ID Mask.  <a href="group__srio__v1__0.html#ga6541e592e664f2549721d2073626dc91">More...</a><br /></td></tr>
<tr class="separator:ga6541e592e664f2549721d2073626dc91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7792cee1d15dc5648c3d889cf0a3a8a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga7792cee1d15dc5648c3d889cf0a3a8a8">XSRIO_PORT_N_ACKID_CSR_OSACKID_MASK</a>&#160;&#160;&#160;0x00003F00</td></tr>
<tr class="memdesc:ga7792cee1d15dc5648c3d889cf0a3a8a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Out Standing ACK ID Mask.  <a href="group__srio__v1__0.html#ga7792cee1d15dc5648c3d889cf0a3a8a8">More...</a><br /></td></tr>
<tr class="separator:ga7792cee1d15dc5648c3d889cf0a3a8a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8acb5233083f47870eddd512acf461cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8acb5233083f47870eddd512acf461cd">XSRIO_PORT_N_ACKID_CSR_IBACKID_MASK</a>&#160;&#160;&#160;0x3F000000</td></tr>
<tr class="memdesc:ga8acb5233083f47870eddd512acf461cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">In bound ACK ID Mask.  <a href="group__srio__v1__0.html#ga8acb5233083f47870eddd512acf461cd">More...</a><br /></td></tr>
<tr class="separator:ga8acb5233083f47870eddd512acf461cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab22ac5185816e99ebaf0d6ebca184633"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab22ac5185816e99ebaf0d6ebca184633">XSRIO_PORT_N_ACKID_CSR_CLSACKID_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gab22ac5185816e99ebaf0d6ebca184633"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear Outstanding ACK ID Mask.  <a href="group__srio__v1__0.html#gab22ac5185816e99ebaf0d6ebca184633">More...</a><br /></td></tr>
<tr class="separator:gab22ac5185816e99ebaf0d6ebca184633"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabadb3622d68d65a1ff9d08a7bd754620"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gabadb3622d68d65a1ff9d08a7bd754620">XSRIO_PORT_N_ACKID_CSR_RESET_OBACKID_MASK</a>&#160;&#160;&#160;0xFFFFFFC0</td></tr>
<tr class="memdesc:gabadb3622d68d65a1ff9d08a7bd754620"><td class="mdescLeft">&#160;</td><td class="mdescRight">Out bound ACK ID Reset Mask.  <a href="group__srio__v1__0.html#gabadb3622d68d65a1ff9d08a7bd754620">More...</a><br /></td></tr>
<tr class="separator:gabadb3622d68d65a1ff9d08a7bd754620"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8e80519afd40400fcc74f268a7a2e7a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab8e80519afd40400fcc74f268a7a2e7a">XSRIO_PORT_N_ACKID_CSR_RESET_IBACKID_MASK</a>&#160;&#160;&#160;0xC0FFFFFF</td></tr>
<tr class="memdesc:gab8e80519afd40400fcc74f268a7a2e7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">In bound ACK ID Reset Mask.  <a href="group__srio__v1__0.html#gab8e80519afd40400fcc74f268a7a2e7a">More...</a><br /></td></tr>
<tr class="separator:gab8e80519afd40400fcc74f268a7a2e7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b3e4ea25cec8c9876433d60720c2b9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8b3e4ea25cec8c9876433d60720c2b9b">XSRIO_PORT_N_ACKID_CSR_IBACKID_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:ga8b3e4ea25cec8c9876433d60720c2b9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">In bound ACK ID shift.  <a href="group__srio__v1__0.html#ga8b3e4ea25cec8c9876433d60720c2b9b">More...</a><br /></td></tr>
<tr class="separator:ga8b3e4ea25cec8c9876433d60720c2b9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n Error and Status CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_ERR_STS_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga234db9291dc39e328f3ff1bebf917fa2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga234db9291dc39e328f3ff1bebf917fa2">XSRIO_PORT_N_ERR_STS_CSR_PUINT_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga234db9291dc39e328f3ff1bebf917fa2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port un-initialized Mask.  <a href="group__srio__v1__0.html#ga234db9291dc39e328f3ff1bebf917fa2">More...</a><br /></td></tr>
<tr class="separator:ga234db9291dc39e328f3ff1bebf917fa2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadcf7a7ca097eec0183f276bf5c1f4404"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gadcf7a7ca097eec0183f276bf5c1f4404">XSRIO_PORT_N_ERR_STS_CSR_POK_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gadcf7a7ca097eec0183f276bf5c1f4404"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Ok Mask.  <a href="group__srio__v1__0.html#gadcf7a7ca097eec0183f276bf5c1f4404">More...</a><br /></td></tr>
<tr class="separator:gadcf7a7ca097eec0183f276bf5c1f4404"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae032e5dfd92bf02d69d6418fdec726ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gae032e5dfd92bf02d69d6418fdec726ac">XSRIO_PORT_N_ERR_STS_CSR_PERR_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gae032e5dfd92bf02d69d6418fdec726ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Error Mask.  <a href="group__srio__v1__0.html#gae032e5dfd92bf02d69d6418fdec726ac">More...</a><br /></td></tr>
<tr class="separator:gae032e5dfd92bf02d69d6418fdec726ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae45a1ba2eeebde57054cf37120fe2237"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gae45a1ba2eeebde57054cf37120fe2237">XSRIO_PORT_N_ERR_STS_CSR_IERRS_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gae45a1ba2eeebde57054cf37120fe2237"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Error stopped Mask.  <a href="group__srio__v1__0.html#gae45a1ba2eeebde57054cf37120fe2237">More...</a><br /></td></tr>
<tr class="separator:gae45a1ba2eeebde57054cf37120fe2237"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1355c4f2e34002d8aeaaf75e98144db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gac1355c4f2e34002d8aeaaf75e98144db">XSRIO_PORT_N_ERR_STS_CSR_IERRE_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:gac1355c4f2e34002d8aeaaf75e98144db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Error encountered Mask.  <a href="group__srio__v1__0.html#gac1355c4f2e34002d8aeaaf75e98144db">More...</a><br /></td></tr>
<tr class="separator:gac1355c4f2e34002d8aeaaf75e98144db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga34888996e940b1315a2d300b0ebf11bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga34888996e940b1315a2d300b0ebf11bd">XSRIO_PORT_N_ERR_STS_CSR_IRTS_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga34888996e940b1315a2d300b0ebf11bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Retry Stopped Mask.  <a href="group__srio__v1__0.html#ga34888996e940b1315a2d300b0ebf11bd">More...</a><br /></td></tr>
<tr class="separator:ga34888996e940b1315a2d300b0ebf11bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97da464bd6fda540c412e054eaf8c25e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga97da464bd6fda540c412e054eaf8c25e">XSRIO_PORT_N_ERR_STS_CSR_OERRS_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:ga97da464bd6fda540c412e054eaf8c25e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output error Stopped Mask.  <a href="group__srio__v1__0.html#ga97da464bd6fda540c412e054eaf8c25e">More...</a><br /></td></tr>
<tr class="separator:ga97da464bd6fda540c412e054eaf8c25e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb39b8809156c77d761cce5b8a642801"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gacb39b8809156c77d761cce5b8a642801">XSRIO_PORT_N_ERR_STS_CSR_OERRE_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:gacb39b8809156c77d761cce5b8a642801"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output error encountered Mask.  <a href="group__srio__v1__0.html#gacb39b8809156c77d761cce5b8a642801">More...</a><br /></td></tr>
<tr class="separator:gacb39b8809156c77d761cce5b8a642801"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ba6f3445bbb730ed03ecd5497ff7c4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1ba6f3445bbb730ed03ecd5497ff7c4a">XSRIO_PORT_N_ERR_STS_CSR_ORTS_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:ga1ba6f3445bbb730ed03ecd5497ff7c4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Retry Stopped Mask.  <a href="group__srio__v1__0.html#ga1ba6f3445bbb730ed03ecd5497ff7c4a">More...</a><br /></td></tr>
<tr class="separator:ga1ba6f3445bbb730ed03ecd5497ff7c4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4a4136f5039f2c55eb1040de7cb9104"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaf4a4136f5039f2c55eb1040de7cb9104">XSRIO_PORT_N_ERR_STS_CSR_OR_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:gaf4a4136f5039f2c55eb1040de7cb9104"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Retried Mask.  <a href="group__srio__v1__0.html#gaf4a4136f5039f2c55eb1040de7cb9104">More...</a><br /></td></tr>
<tr class="separator:gaf4a4136f5039f2c55eb1040de7cb9104"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31eadac3a28f8c827860ff9789e7d9bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga31eadac3a28f8c827860ff9789e7d9bb">XSRIO_PORT_N_ERR_STS_CSR_ORE_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:ga31eadac3a28f8c827860ff9789e7d9bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Retry Encountered Mask.  <a href="group__srio__v1__0.html#ga31eadac3a28f8c827860ff9789e7d9bb">More...</a><br /></td></tr>
<tr class="separator:ga31eadac3a28f8c827860ff9789e7d9bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0437a4bd498d1ab8e2986f45e98b5d6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga0437a4bd498d1ab8e2986f45e98b5d6b">XSRIO_PORT_N_ERR_STS_CSR_FLOWCNTL_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:ga0437a4bd498d1ab8e2986f45e98b5d6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flow Control Mode Mask.  <a href="group__srio__v1__0.html#ga0437a4bd498d1ab8e2986f45e98b5d6b">More...</a><br /></td></tr>
<tr class="separator:ga0437a4bd498d1ab8e2986f45e98b5d6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gada0f67e25592b9db54601a3b5ff86fd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gada0f67e25592b9db54601a3b5ff86fd3">XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQ_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:gada0f67e25592b9db54601a3b5ff86fd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Idle sequence Mask.  <a href="group__srio__v1__0.html#gada0f67e25592b9db54601a3b5ff86fd3">More...</a><br /></td></tr>
<tr class="separator:gada0f67e25592b9db54601a3b5ff86fd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cb51ad2cc95cee2fbf35dc3dabd3c6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga0cb51ad2cc95cee2fbf35dc3dabd3c6c">XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQE_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga0cb51ad2cc95cee2fbf35dc3dabd3c6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Idle sequence 2 Enable Mask.  <a href="group__srio__v1__0.html#ga0cb51ad2cc95cee2fbf35dc3dabd3c6c">More...</a><br /></td></tr>
<tr class="separator:ga0cb51ad2cc95cee2fbf35dc3dabd3c6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4424028c2a3e2e2ec7efe9a7e7a34d36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4424028c2a3e2e2ec7efe9a7e7a34d36">XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQS_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga4424028c2a3e2e2ec7efe9a7e7a34d36"><td class="mdescLeft">&#160;</td><td class="mdescRight">Idle sequence 2 support Mask.  <a href="group__srio__v1__0.html#ga4424028c2a3e2e2ec7efe9a7e7a34d36">More...</a><br /></td></tr>
<tr class="separator:ga4424028c2a3e2e2ec7efe9a7e7a34d36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72cb3e32c415ed1ad9bf901ed4738c3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga72cb3e32c415ed1ad9bf901ed4738c3b">XSRIO_PORT_N_ERR_STS_CSR_ERR_ALL_MASK</a>&#160;&#160;&#160;0x001FFF07</td></tr>
<tr class="memdesc:ga72cb3e32c415ed1ad9bf901ed4738c3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Errors Mask.  <a href="group__srio__v1__0.html#ga72cb3e32c415ed1ad9bf901ed4738c3b">More...</a><br /></td></tr>
<tr class="separator:ga72cb3e32c415ed1ad9bf901ed4738c3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Port n Control CSR bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_PORT_N_CTL_CSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga402577166192eafac28530c4dc01ca8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga402577166192eafac28530c4dc01ca8a">XSRIO_PORT_N_CTL_CSR_PTYPE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga402577166192eafac28530c4dc01ca8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Type Mask.  <a href="group__srio__v1__0.html#ga402577166192eafac28530c4dc01ca8a">More...</a><br /></td></tr>
<tr class="separator:ga402577166192eafac28530c4dc01ca8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab34ac90f0661f0f01b419ddba140fefa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab34ac90f0661f0f01b419ddba140fefa">XSRIO_PORT_N_CTL_CSR_EPWDS_MASK</a>&#160;&#160;&#160;0x00003000</td></tr>
<tr class="memdesc:gab34ac90f0661f0f01b419ddba140fefa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Port Width Support Mask.  <a href="group__srio__v1__0.html#gab34ac90f0661f0f01b419ddba140fefa">More...</a><br /></td></tr>
<tr class="separator:gab34ac90f0661f0f01b419ddba140fefa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaade15cdc9ab71ab8c0593c04b026ea80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaade15cdc9ab71ab8c0593c04b026ea80">XSRIO_PORT_N_CTL_CSR_EPWOR_MASK</a>&#160;&#160;&#160;0x0000C000</td></tr>
<tr class="memdesc:gaade15cdc9ab71ab8c0593c04b026ea80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Port Width Override Mask.  <a href="group__srio__v1__0.html#gaade15cdc9ab71ab8c0593c04b026ea80">More...</a><br /></td></tr>
<tr class="separator:gaade15cdc9ab71ab8c0593c04b026ea80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5e4697d8469fa671713a7d0f948410e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab5e4697d8469fa671713a7d0f948410e">XSRIO_PORT_N_CTL_CSR_ENUMB_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:gab5e4697d8469fa671713a7d0f948410e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enumeration Boundary Mask.  <a href="group__srio__v1__0.html#gab5e4697d8469fa671713a7d0f948410e">More...</a><br /></td></tr>
<tr class="separator:gab5e4697d8469fa671713a7d0f948410e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0bc827ab57560c61d8ddb6b4599ae66d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga0bc827ab57560c61d8ddb6b4599ae66d">XSRIO_PORT_N_CTL_CSR_MCENT_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga0bc827ab57560c61d8ddb6b4599ae66d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi-cast Event Participant Mask.  <a href="group__srio__v1__0.html#ga0bc827ab57560c61d8ddb6b4599ae66d">More...</a><br /></td></tr>
<tr class="separator:ga0bc827ab57560c61d8ddb6b4599ae66d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf09fa214f30591f55b3838068f51e96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaaf09fa214f30591f55b3838068f51e96">XSRIO_PORT_N_CTL_CSR_ERRD_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:gaaf09fa214f30591f55b3838068f51e96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Checking Disable Mask.  <a href="group__srio__v1__0.html#gaaf09fa214f30591f55b3838068f51e96">More...</a><br /></td></tr>
<tr class="separator:gaaf09fa214f30591f55b3838068f51e96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8fc9a44909fe3572334dd3910718c71f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8fc9a44909fe3572334dd3910718c71f">XSRIO_PORT_N_CTL_CSR_IPE_MASK</a>&#160;&#160;&#160;0x00200000</td></tr>
<tr class="memdesc:ga8fc9a44909fe3572334dd3910718c71f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input port enable Mask.  <a href="group__srio__v1__0.html#ga8fc9a44909fe3572334dd3910718c71f">More...</a><br /></td></tr>
<tr class="separator:ga8fc9a44909fe3572334dd3910718c71f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8d36af1fe0f7656ac68e9d9cfdb03749"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8d36af1fe0f7656ac68e9d9cfdb03749">XSRIO_PORT_N_CTL_CSR_OPE_MASK</a>&#160;&#160;&#160;0x00400000</td></tr>
<tr class="memdesc:ga8d36af1fe0f7656ac68e9d9cfdb03749"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output port enable Mask.  <a href="group__srio__v1__0.html#ga8d36af1fe0f7656ac68e9d9cfdb03749">More...</a><br /></td></tr>
<tr class="separator:ga8d36af1fe0f7656ac68e9d9cfdb03749"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab12c5ccde74b09b8a85e1d656eaf9135"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab12c5ccde74b09b8a85e1d656eaf9135">XSRIO_PORT_N_CTL_CSR_PD_MASK</a>&#160;&#160;&#160;0x00800000</td></tr>
<tr class="memdesc:gab12c5ccde74b09b8a85e1d656eaf9135"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output port disable Mask.  <a href="group__srio__v1__0.html#gab12c5ccde74b09b8a85e1d656eaf9135">More...</a><br /></td></tr>
<tr class="separator:gab12c5ccde74b09b8a85e1d656eaf9135"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gada34aa1e1fa5c40f1fa47aadce896ca6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gada34aa1e1fa5c40f1fa47aadce896ca6">XSRIO_PORT_N_CTL_CSR_PWO_MASK</a>&#160;&#160;&#160;0x07000000</td></tr>
<tr class="memdesc:gada34aa1e1fa5c40f1fa47aadce896ca6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port width Override Mask.  <a href="group__srio__v1__0.html#gada34aa1e1fa5c40f1fa47aadce896ca6">More...</a><br /></td></tr>
<tr class="separator:gada34aa1e1fa5c40f1fa47aadce896ca6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e7acaa5c3c152ded875097ff2fdb658"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1e7acaa5c3c152ded875097ff2fdb658">XSRIO_PORT_N_CTL_CSR_RESET_PWO_MASK</a>&#160;&#160;&#160;0xF8FFFFFF</td></tr>
<tr class="memdesc:ga1e7acaa5c3c152ded875097ff2fdb658"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port width Override Reset Mask.  <a href="group__srio__v1__0.html#ga1e7acaa5c3c152ded875097ff2fdb658">More...</a><br /></td></tr>
<tr class="separator:ga1e7acaa5c3c152ded875097ff2fdb658"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga445ed5a9d8f4de221f17c265e0b89c2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga445ed5a9d8f4de221f17c265e0b89c2b">XSRIO_PORT_N_CTL_CSR_IPW_MASK</a>&#160;&#160;&#160;0x38000000</td></tr>
<tr class="memdesc:ga445ed5a9d8f4de221f17c265e0b89c2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialized Port width Mask.  <a href="group__srio__v1__0.html#ga445ed5a9d8f4de221f17c265e0b89c2b">More...</a><br /></td></tr>
<tr class="separator:ga445ed5a9d8f4de221f17c265e0b89c2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga250610669bf930864ff1feb24457cc03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga250610669bf930864ff1feb24457cc03">XSRIO_PORT_N_CTL_CSR_PW_MASK</a>&#160;&#160;&#160;0xc0000000</td></tr>
<tr class="memdesc:ga250610669bf930864ff1feb24457cc03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port width Mask.  <a href="group__srio__v1__0.html#ga250610669bf930864ff1feb24457cc03">More...</a><br /></td></tr>
<tr class="separator:ga250610669bf930864ff1feb24457cc03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga364330b68240054841422bcc2144ad56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga364330b68240054841422bcc2144ad56">XSRIO_PORT_N_CTL_CSR_STATUS_ALL_MASK</a>&#160;&#160;&#160;0x00F00000</td></tr>
<tr class="memdesc:ga364330b68240054841422bcc2144ad56"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Status All Mask.  <a href="group__srio__v1__0.html#ga364330b68240054841422bcc2144ad56">More...</a><br /></td></tr>
<tr class="separator:ga364330b68240054841422bcc2144ad56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55777eb3881e2b939ba8de77a16c62d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga55777eb3881e2b939ba8de77a16c62d6">XSRIO_PORT_N_CTL_CSR_PWO_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:ga55777eb3881e2b939ba8de77a16c62d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port width Override Shift.  <a href="group__srio__v1__0.html#ga55777eb3881e2b939ba8de77a16c62d6">More...</a><br /></td></tr>
<tr class="separator:ga55777eb3881e2b939ba8de77a16c62d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga758e575a915495f7a319fd4e89eeae14"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga758e575a915495f7a319fd4e89eeae14">XSRIO_PORT_N_CTL_CSR_PW_SHIFT</a>&#160;&#160;&#160;30</td></tr>
<tr class="memdesc:ga758e575a915495f7a319fd4e89eeae14"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port width Shift.  <a href="group__srio__v1__0.html#ga758e575a915495f7a319fd4e89eeae14">More...</a><br /></td></tr>
<tr class="separator:ga758e575a915495f7a319fd4e89eeae14"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">LP -Serial Lane Register Block Header bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SL_HEADER_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga3eb2acf6b38897bb09f50f287ede671f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga3eb2acf6b38897bb09f50f287ede671f">XSRIO_SL_HEADER_EFID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga3eb2acf6b38897bb09f50f287ede671f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features ID Mask.  <a href="group__srio__v1__0.html#ga3eb2acf6b38897bb09f50f287ede671f">More...</a><br /></td></tr>
<tr class="separator:ga3eb2acf6b38897bb09f50f287ede671f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8ff82d1b0be608c51ff0429e823f7a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gad8ff82d1b0be608c51ff0429e823f7a1">XSRIO_SL_HEADER_EFP_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:gad8ff82d1b0be608c51ff0429e823f7a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features Pointer Mask.  <a href="group__srio__v1__0.html#gad8ff82d1b0be608c51ff0429e823f7a1">More...</a><br /></td></tr>
<tr class="separator:gad8ff82d1b0be608c51ff0429e823f7a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78b48c1d1df27c224b1c46435a55ba6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga78b48c1d1df27c224b1c46435a55ba6f">XSRIO_SL_HEADER_EFP_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga78b48c1d1df27c224b1c46435a55ba6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended Features Pointer Shift.  <a href="group__srio__v1__0.html#ga78b48c1d1df27c224b1c46435a55ba6f">More...</a><br /></td></tr>
<tr class="separator:ga78b48c1d1df27c224b1c46435a55ba6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">LP -Seral Lane n Status 0 CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SLS0_CSR(x) register. </p>
</div></td></tr>
<tr class="memitem:gab68b92bec3fa239036763f436f809a71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab68b92bec3fa239036763f436f809a71">XSRIO_SLS0_CSR_PORT_NUM_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:gab68b92bec3fa239036763f436f809a71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Number Mask.  <a href="group__srio__v1__0.html#gab68b92bec3fa239036763f436f809a71">More...</a><br /></td></tr>
<tr class="separator:gab68b92bec3fa239036763f436f809a71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bed2867803ea42900f1baf44e308d56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga3bed2867803ea42900f1baf44e308d56">XSRIO_SLS0_CSR_LANE_NUM_MASK</a>&#160;&#160;&#160;0x00F00000</td></tr>
<tr class="memdesc:ga3bed2867803ea42900f1baf44e308d56"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane Number Mask.  <a href="group__srio__v1__0.html#ga3bed2867803ea42900f1baf44e308d56">More...</a><br /></td></tr>
<tr class="separator:ga3bed2867803ea42900f1baf44e308d56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2690a0fa715e0615bf2be13d20a47f52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2690a0fa715e0615bf2be13d20a47f52">XSRIO_SLS0_CSR_TRANSMIT_TYPE_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga2690a0fa715e0615bf2be13d20a47f52"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter Type Mask.  <a href="group__srio__v1__0.html#ga2690a0fa715e0615bf2be13d20a47f52">More...</a><br /></td></tr>
<tr class="separator:ga2690a0fa715e0615bf2be13d20a47f52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8d085c3923b87d929ccdc9ad4eecda8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gae8d085c3923b87d929ccdc9ad4eecda8">XSRIO_SLS0_CSR_TRANSMIT_MODE_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:gae8d085c3923b87d929ccdc9ad4eecda8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter Mode Mask.  <a href="group__srio__v1__0.html#gae8d085c3923b87d929ccdc9ad4eecda8">More...</a><br /></td></tr>
<tr class="separator:gae8d085c3923b87d929ccdc9ad4eecda8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4fea8f1bf3d1e64b37dc633ce497fe5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gab4fea8f1bf3d1e64b37dc633ce497fe5">XSRIO_SLS0_CSR_RCV_INPUT_INV_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:gab4fea8f1bf3d1e64b37dc633ce497fe5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receiver Input Inverted Mask.  <a href="group__srio__v1__0.html#gab4fea8f1bf3d1e64b37dc633ce497fe5">More...</a><br /></td></tr>
<tr class="separator:gab4fea8f1bf3d1e64b37dc633ce497fe5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffe5ce5b2a6b694b3629774b5a5773c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaffe5ce5b2a6b694b3629774b5a5773c6">XSRIO_SLS0_CSR_RCV_TRAINED_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gaffe5ce5b2a6b694b3629774b5a5773c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receiver Trained Mask.  <a href="group__srio__v1__0.html#gaffe5ce5b2a6b694b3629774b5a5773c6">More...</a><br /></td></tr>
<tr class="separator:gaffe5ce5b2a6b694b3629774b5a5773c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6dd75e438c1df75651de45b0502c2b29"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga6dd75e438c1df75651de45b0502c2b29">XSRIO_SLS0_CSR_RCVLANE_SYNC_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:ga6dd75e438c1df75651de45b0502c2b29"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Lane Sync Mask.  <a href="group__srio__v1__0.html#ga6dd75e438c1df75651de45b0502c2b29">More...</a><br /></td></tr>
<tr class="separator:ga6dd75e438c1df75651de45b0502c2b29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b41f9c91392bc40e8d375dcb7288182"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4b41f9c91392bc40e8d375dcb7288182">XSRIO_SLS0_CSR_RCVLANE_RDY_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga4b41f9c91392bc40e8d375dcb7288182"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Lane Ready Mask.  <a href="group__srio__v1__0.html#ga4b41f9c91392bc40e8d375dcb7288182">More...</a><br /></td></tr>
<tr class="separator:ga4b41f9c91392bc40e8d375dcb7288182"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga735fded4f8506dc560fcce58190e8792"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga735fded4f8506dc560fcce58190e8792">XSRIO_SLS0_CSR_DECODING_ERRORS_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:ga735fded4f8506dc560fcce58190e8792"><td class="mdescLeft">&#160;</td><td class="mdescRight">8B/10B Decoding errors Mask  <a href="group__srio__v1__0.html#ga735fded4f8506dc560fcce58190e8792">More...</a><br /></td></tr>
<tr class="separator:ga735fded4f8506dc560fcce58190e8792"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb7c023efc6c842c7271fe4c36557b23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gacb7c023efc6c842c7271fe4c36557b23">XSRIO_SLS0_CSR_LANESYNC_CHAN_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gacb7c023efc6c842c7271fe4c36557b23"><td class="mdescLeft">&#160;</td><td class="mdescRight">lane_sync state change Mask  <a href="group__srio__v1__0.html#gacb7c023efc6c842c7271fe4c36557b23">More...</a><br /></td></tr>
<tr class="separator:gacb7c023efc6c842c7271fe4c36557b23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga558fa123f519f32cfaacf33e2855bd6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga558fa123f519f32cfaacf33e2855bd6c">XSRIO_SLS0_CSR_RCVTRAINED_CHAN_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga558fa123f519f32cfaacf33e2855bd6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">rcvr_train state changed Mask  <a href="group__srio__v1__0.html#ga558fa123f519f32cfaacf33e2855bd6c">More...</a><br /></td></tr>
<tr class="separator:ga558fa123f519f32cfaacf33e2855bd6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2aa0c6a858135dc0b35f7bb54f098525"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2aa0c6a858135dc0b35f7bb54f098525">XSRIO_SLS0_CSR_STAT1_IMP_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga2aa0c6a858135dc0b35f7bb54f098525"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status 1 CSR Implemented Mask.  <a href="group__srio__v1__0.html#ga2aa0c6a858135dc0b35f7bb54f098525">More...</a><br /></td></tr>
<tr class="separator:ga2aa0c6a858135dc0b35f7bb54f098525"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab5ffaf0b2b1dafd570be459fded1e60"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSRIO_SLS0_CSR_DECODING_ERRORS_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:gaab5ffaf0b2b1dafd570be459fded1e60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">LP -Seral Lane n Status 1 CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_SLS1_CSR(x) register. </p>
</div></td></tr>
<tr class="memitem:ga643be9256cb17c9b9ff76e0e01069549"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga643be9256cb17c9b9ff76e0e01069549">XSRIO_SLS1_CSR_SCRDSCR_EN_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ga643be9256cb17c9b9ff76e0e01069549"><td class="mdescLeft">&#160;</td><td class="mdescRight">Connected port Scrambling/Descrambling Enabled Mask.  <a href="group__srio__v1__0.html#ga643be9256cb17c9b9ff76e0e01069549">More...</a><br /></td></tr>
<tr class="separator:ga643be9256cb17c9b9ff76e0e01069549"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15956fcb93d355ff905546c5d49233f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga15956fcb93d355ff905546c5d49233f4">XSRIO_SLS1_CSR_CPTEIS_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:ga15956fcb93d355ff905546c5d49233f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Connected port transmit Emphasis Tap(+1) Status Mask.  <a href="group__srio__v1__0.html#ga15956fcb93d355ff905546c5d49233f4">More...</a><br /></td></tr>
<tr class="separator:ga15956fcb93d355ff905546c5d49233f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1777189a80a15658e80d3a3844ee4c9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1777189a80a15658e80d3a3844ee4c9e">XSRIO_SLS1_CSR_CPTEDS_MASK</a>&#160;&#160;&#160;0x000C0000</td></tr>
<tr class="memdesc:ga1777189a80a15658e80d3a3844ee4c9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Connected port transmit Emphasis Tap(-1) Status Mask.  <a href="group__srio__v1__0.html#ga1777189a80a15658e80d3a3844ee4c9e">More...</a><br /></td></tr>
<tr class="separator:ga1777189a80a15658e80d3a3844ee4c9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97eaede8cdfe84de3ad7c97bdcb4a7d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga97eaede8cdfe84de3ad7c97bdcb4a7d8">XSRIO_SLS1_CSR_LANENUM_MASK</a>&#160;&#160;&#160;0x00F00000</td></tr>
<tr class="memdesc:ga97eaede8cdfe84de3ad7c97bdcb4a7d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane number within connected port.  <a href="group__srio__v1__0.html#ga97eaede8cdfe84de3ad7c97bdcb4a7d8">More...</a><br /></td></tr>
<tr class="separator:ga97eaede8cdfe84de3ad7c97bdcb4a7d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf12499191f757d9080763a9ac15f3b0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaf12499191f757d9080763a9ac15f3b0e">XSRIO_SLS1_CSR_RXPORT_WIDTH_MASK</a>&#160;&#160;&#160;0x07000000</td></tr>
<tr class="memdesc:gaf12499191f757d9080763a9ac15f3b0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive port width Mask.  <a href="group__srio__v1__0.html#gaf12499191f757d9080763a9ac15f3b0e">More...</a><br /></td></tr>
<tr class="separator:gaf12499191f757d9080763a9ac15f3b0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff7960a844f78343ca547df971a6854b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaff7960a844f78343ca547df971a6854b">XSRIO_SLS1_CSR_CPLR_TRAINED_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:gaff7960a844f78343ca547df971a6854b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Connected port lane Receiver trained Mask.  <a href="group__srio__v1__0.html#gaff7960a844f78343ca547df971a6854b">More...</a><br /></td></tr>
<tr class="separator:gaff7960a844f78343ca547df971a6854b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga390ed21b4c733c1fdf532b2380d4c239"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga390ed21b4c733c1fdf532b2380d4c239">XSRIO_SLS1_CSR_IMPDEFINED_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:ga390ed21b4c733c1fdf532b2380d4c239"><td class="mdescLeft">&#160;</td><td class="mdescRight">Implementation defined Mask.  <a href="group__srio__v1__0.html#ga390ed21b4c733c1fdf532b2380d4c239">More...</a><br /></td></tr>
<tr class="separator:ga390ed21b4c733c1fdf532b2380d4c239"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae975e444f9d169cb0ba11c0b072950ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gae975e444f9d169cb0ba11c0b072950ee">XSRIO_SLS1_CSR_VALCHANGED_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:gae975e444f9d169cb0ba11c0b072950ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values Changed Mask.  <a href="group__srio__v1__0.html#gae975e444f9d169cb0ba11c0b072950ee">More...</a><br /></td></tr>
<tr class="separator:gae975e444f9d169cb0ba11c0b072950ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga62f404e57a27d90f885acf532301b637"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga62f404e57a27d90f885acf532301b637">XSRIO_SLS1_CSR_IDLE2_INFO_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga62f404e57a27d90f885acf532301b637"><td class="mdescLeft">&#160;</td><td class="mdescRight">IDLE2 Information Current Mask.  <a href="group__srio__v1__0.html#ga62f404e57a27d90f885acf532301b637">More...</a><br /></td></tr>
<tr class="separator:ga62f404e57a27d90f885acf532301b637"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ed6529eb42c4a517d08cc65cc388d84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga9ed6529eb42c4a517d08cc65cc388d84">XSRIO_SLS1_CSR_IDLE2_REC_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga9ed6529eb42c4a517d08cc65cc388d84"><td class="mdescLeft">&#160;</td><td class="mdescRight">IDLE2 Received Mask.  <a href="group__srio__v1__0.html#ga9ed6529eb42c4a517d08cc65cc388d84">More...</a><br /></td></tr>
<tr class="separator:ga9ed6529eb42c4a517d08cc65cc388d84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Water Mark CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_IMP_WCSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga53adbebbf16c0da5ca8d90167e9b9c57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga53adbebbf16c0da5ca8d90167e9b9c57">XSRIO_IMP_WCSR_WM2_MASK</a>&#160;&#160;&#160;0x003F0000</td></tr>
<tr class="memdesc:ga53adbebbf16c0da5ca8d90167e9b9c57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Water Mark 2 Mask.  <a href="group__srio__v1__0.html#ga53adbebbf16c0da5ca8d90167e9b9c57">More...</a><br /></td></tr>
<tr class="separator:ga53adbebbf16c0da5ca8d90167e9b9c57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06ccd785f2726efe3a060c0a914c66cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga06ccd785f2726efe3a060c0a914c66cd">XSRIO_IMP_WCSR_WM1_MASK</a>&#160;&#160;&#160;0x00003F00</td></tr>
<tr class="memdesc:ga06ccd785f2726efe3a060c0a914c66cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Water Mark 1 Mask.  <a href="group__srio__v1__0.html#ga06ccd785f2726efe3a060c0a914c66cd">More...</a><br /></td></tr>
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<tr class="memitem:ga614ee4a2172a0c12d709b002a20fbeef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga614ee4a2172a0c12d709b002a20fbeef">XSRIO_IMP_WCSR_WM0_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:ga614ee4a2172a0c12d709b002a20fbeef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Water Mark 0 Mask.  <a href="group__srio__v1__0.html#ga614ee4a2172a0c12d709b002a20fbeef">More...</a><br /></td></tr>
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<tr class="memitem:ga00a76a62641f17c8c9e4d76f2b1e6168"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga00a76a62641f17c8c9e4d76f2b1e6168">XSRIO_IMP_WCSR_WM1_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga00a76a62641f17c8c9e4d76f2b1e6168"><td class="mdescLeft">&#160;</td><td class="mdescRight">Water Mark 1 Shift.  <a href="group__srio__v1__0.html#ga00a76a62641f17c8c9e4d76f2b1e6168">More...</a><br /></td></tr>
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<tr class="memitem:ga238f24ec2ccd7043d83fbd04edcad4bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga238f24ec2ccd7043d83fbd04edcad4bc">XSRIO_IMP_WCSR_WM2_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga238f24ec2ccd7043d83fbd04edcad4bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Water Mark 2 Shift.  <a href="group__srio__v1__0.html#ga238f24ec2ccd7043d83fbd04edcad4bc">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Buffer Control CSRS bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_IMP_BCSR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:gaad417ab7b7dd1b2126a64fc2919a3734"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gaad417ab7b7dd1b2126a64fc2919a3734">XSRIO_IMP_BCSR_RXFLOW_CNTLONLY_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gaad417ab7b7dd1b2126a64fc2919a3734"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Flow Control Only Mask.  <a href="group__srio__v1__0.html#gaad417ab7b7dd1b2126a64fc2919a3734">More...</a><br /></td></tr>
<tr class="separator:gaad417ab7b7dd1b2126a64fc2919a3734"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c307631f4dbe3b506e3497bda77586b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga0c307631f4dbe3b506e3497bda77586b">XSRIO_IMP_BCSR_UNIFIED_CLK_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga0c307631f4dbe3b506e3497bda77586b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Control Mask.  <a href="group__srio__v1__0.html#ga0c307631f4dbe3b506e3497bda77586b">More...</a><br /></td></tr>
<tr class="separator:ga0c307631f4dbe3b506e3497bda77586b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2fee7f23801a2e0b8ce142335a401717"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga2fee7f23801a2e0b8ce142335a401717">XSRIO_IMP_BCSR_TX_FLOW_CNTL_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:ga2fee7f23801a2e0b8ce142335a401717"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Flow Control Mask.  <a href="group__srio__v1__0.html#ga2fee7f23801a2e0b8ce142335a401717">More...</a><br /></td></tr>
<tr class="separator:ga2fee7f23801a2e0b8ce142335a401717"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8f753d02157a46e2feb752325fa8fa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#gad8f753d02157a46e2feb752325fa8fa9">XSRIO_IMP_BCSR_TXREQ_REORDER_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:gad8f753d02157a46e2feb752325fa8fa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Request Reorder Mask.  <a href="group__srio__v1__0.html#gad8f753d02157a46e2feb752325fa8fa9">More...</a><br /></td></tr>
<tr class="separator:gad8f753d02157a46e2feb752325fa8fa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c58f4eff4ec070291fc83b76351a73c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga8c58f4eff4ec070291fc83b76351a73c">XSRIO_IMP_BCSR_TXSIZE_MASK</a>&#160;&#160;&#160;0x07FF0000</td></tr>
<tr class="memdesc:ga8c58f4eff4ec070291fc83b76351a73c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx size Mask.  <a href="group__srio__v1__0.html#ga8c58f4eff4ec070291fc83b76351a73c">More...</a><br /></td></tr>
<tr class="separator:ga8c58f4eff4ec070291fc83b76351a73c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c3f8e97192bb4fa1ef6de5698663d63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga1c3f8e97192bb4fa1ef6de5698663d63">XSRIO_IMP_BCSR_FRX_FLOW_CNTL_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ga1c3f8e97192bb4fa1ef6de5698663d63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Force Rx flow Control Mask.  <a href="group__srio__v1__0.html#ga1c3f8e97192bb4fa1ef6de5698663d63">More...</a><br /></td></tr>
<tr class="separator:ga1c3f8e97192bb4fa1ef6de5698663d63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga335241657626eab68188c0d505572c35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga335241657626eab68188c0d505572c35">XSRIO_IMP_BCSR_RXSIZE_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:ga335241657626eab68188c0d505572c35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx size Mask.  <a href="group__srio__v1__0.html#ga335241657626eab68188c0d505572c35">More...</a><br /></td></tr>
<tr class="separator:ga335241657626eab68188c0d505572c35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04e3e69ddd5ca32d49b7177773cd4740"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga04e3e69ddd5ca32d49b7177773cd4740">XSRIO_IMP_BCSR_TXSIZE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga04e3e69ddd5ca32d49b7177773cd4740"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx size shift.  <a href="group__srio__v1__0.html#ga04e3e69ddd5ca32d49b7177773cd4740">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Maintenance Request Information Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XSRIO_IMP_MRIR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga6fd471211a93073029bfcdcd7de4ddef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga6fd471211a93073029bfcdcd7de4ddef">XSRIO_IMP_MRIR_REQ_TID_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:ga6fd471211a93073029bfcdcd7de4ddef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Request TID Mask.  <a href="group__srio__v1__0.html#ga6fd471211a93073029bfcdcd7de4ddef">More...</a><br /></td></tr>
<tr class="separator:ga6fd471211a93073029bfcdcd7de4ddef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a5e50909869ab789a272b6e1b93a2be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4a5e50909869ab789a272b6e1b93a2be">XSRIO_IMP_MRIR_REQ_PRIO_MASK</a>&#160;&#160;&#160;0x00060000</td></tr>
<tr class="memdesc:ga4a5e50909869ab789a272b6e1b93a2be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Request Priority Mask.  <a href="group__srio__v1__0.html#ga4a5e50909869ab789a272b6e1b93a2be">More...</a><br /></td></tr>
<tr class="separator:ga4a5e50909869ab789a272b6e1b93a2be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga114b6719c2e1043ef79c009fead1b28d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga114b6719c2e1043ef79c009fead1b28d">XSRIO_IMP_MRIR_REQ_CRF_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:ga114b6719c2e1043ef79c009fead1b28d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Request CRF Mask.  <a href="group__srio__v1__0.html#ga114b6719c2e1043ef79c009fead1b28d">More...</a><br /></td></tr>
<tr class="separator:ga114b6719c2e1043ef79c009fead1b28d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b251ca3e20b50fad896a7b93eadd002"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__srio__v1__0.html#ga4b251ca3e20b50fad896a7b93eadd002">XSRIO_IMP_MRIR_REQ_DESTID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga4b251ca3e20b50fad896a7b93eadd002"><td class="mdescLeft">&#160;</td><td class="mdescRight">Request Destination ID Mask.  <a href="group__srio__v1__0.html#ga4b251ca3e20b50fad896a7b93eadd002">More...</a><br /></td></tr>
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<tr class="memitem:gaae865ad4db5328c09c32b1f4105f5276"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSRIO_IMP_MRIR_REQ_PRIO_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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<tr class="memitem:ga73a0d5b6fa6ad54db9f7251a78b0888c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSRIO_IMP_MRIR_REQ_CRF_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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<tr class="memitem:ga55186561b6e59efbe64182bab5ade583"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSRIO_IMP_MRIR_REQ_TID_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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